Hi arnold, i put 2 others screenshots.

The first (screenshot1.png) is normal access by DMA0,1,2. And sequence seem to be:
DMAx :
select AY register
AY inactive
write register
AY inactive
restore previous ay register selection
AY inactive

In my example, i select Ay reg 0 then 3 before DMA access, and you can see the last selected reg (3) is restore after each DMA access
(DMA0 access to Reg8, DMA1 => Reg9, and DMA2 => Reg10)

In my second screenshots (screenshot2.png), i try to selected AY reg by CPU when a DMA access occured. It seem that after DMA access (restore ay register), CPU takes over for some times (about 3µs) then next DMA access ...

+++

PS : sorry for my bad english

Nice pictures

Can you confirm something please?

If DMA 2 is active and DMA 0 and DMA 1 are inactive, What are the timings?

Do we see this:

<no read/dummy read>, <no read/dummy read>, <dma 2 read>

or

<dma 2 read>

What are the actions done for inactive channels?